# -*- coding: utf-8 -*-
"""
 Copyright 2025 NXP

 NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be
 used strictly in accordance with the applicable license terms. By expressly
 accepting such terms or by downloading, installing, activating and/or otherwise
 using the software, you are agreeing that you have read, and that you agree to
 comply with and are bound by, such license terms. If you do not agree to be
 bound by the applicable license terms, then you may not retain, install,
 activate or otherwise use the software.

"""

class CortexRegisters:
    """
    Cortex processor register definitions
    """
    
    # Base addresses from TCL file
    DEBUG_REGISTERS_FIRST = 0x1000
    CORE_REGISTERS_FIRST = 0x2000
    PSR_REGISTERS_FIRST = 0x3000
    VFP_REGISTERS_FIRST = 0x4000
    MISC_REGISTERS_FIRST = 0x6000
    CP_REGISTERS_FIRST = 0x100000
    CP_REGISTERS_64_FIRST = 0x200000
    CP_NS_REGISTERS_FIRST = 0x300000
    CP_NS_REGISTERS_64_FIRST = 0x400000
    CP_HYP_REGISTERS_FIRST = 0x500000
    CP_HYP_REGISTERS_64_FIRST = 0x600000
    
    # Core Registers
    # Formula: core_registers_first + ((mode & 0x1f) << 4) + (reg & 0xf)
    CORE_REGISTERS = {
        "r0": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (0 & 0xf),
        "r1": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (1 & 0xf),
        "r2": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (2 & 0xf),
        "r3": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (3 & 0xf),
        "r4": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (4 & 0xf),
        "r5": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (5 & 0xf),
        "r6": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (6 & 0xf),
        "r7": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (7 & 0xf),
        "r8": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (8 & 0xf),
        "r9": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (9 & 0xf),
        "r10": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (10 & 0xf),
        "r11": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (11 & 0xf),
        "r12": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (12 & 0xf),
        "r13": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (13 & 0xf),
        "r14": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (14 & 0xf),
        "r15": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (15 & 0xf),
        "r8_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (8 & 0xf),
        "r9_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (9 & 0xf),
        "r10_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (10 & 0xf),
        "r11_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (11 & 0xf),
        "r12_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (12 & 0xf),
        "r13_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (13 & 0xf),
        "r14_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (14 & 0xf),
        "r15_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (15 & 0xf),
        "pc": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (15 & 0xf),
        "r8_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (8 & 0xf),
        "r9_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (9 & 0xf),
        "r10_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (10 & 0xf),
        "r11_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (11 & 0xf),
        "r12_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (12 & 0xf),
        "r13_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (13 & 0xf),
        "r14_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (14 & 0xf),
        "r13_svc": CORE_REGISTERS_FIRST + ((0x13 & 0x1f) << 4) + (13 & 0xf),
        "r14_svc": CORE_REGISTERS_FIRST + ((0x13 & 0x1f) << 4) + (14 & 0xf),
        "r13_abt": CORE_REGISTERS_FIRST + ((0x17 & 0x1f) << 4) + (13 & 0xf),
        "r14_abt": CORE_REGISTERS_FIRST + ((0x17 & 0x1f) << 4) + (14 & 0xf),
        "r13_irq": CORE_REGISTERS_FIRST + ((0x12 & 0x1f) << 4) + (13 & 0xf),
        "r14_irq": CORE_REGISTERS_FIRST + ((0x12 & 0x1f) << 4) + (14 & 0xf),
        "r13_und": CORE_REGISTERS_FIRST + ((0x1b & 0x1f) << 4) + (13 & 0xf),
        "r14_und": CORE_REGISTERS_FIRST + ((0x1b & 0x1f) << 4) + (14 & 0xf),
        "r13_mon": CORE_REGISTERS_FIRST + ((0x16 & 0x1f) << 4) + (13 & 0xf),
        "r14_mon": CORE_REGISTERS_FIRST + ((0x16 & 0x1f) << 4) + (14 & 0xf),
        "r13_hyp": CORE_REGISTERS_FIRST + ((0x1a & 0x1f) << 4) + (13 & 0xf),
        "r14_hyp": CORE_REGISTERS_FIRST + ((0x1a & 0x1f) << 4) + (14 & 0xf),
    }
    
    # Program Status Registers
    # Formula: psr_registers_first + (mode & 0x1f)
    PSR_REGISTERS = {
        "cpsr": PSR_REGISTERS_FIRST + (0x1f & 0x1f),
        "spsr_fiq": PSR_REGISTERS_FIRST + (0x11 & 0x1f),
        "spsr_svc": PSR_REGISTERS_FIRST + (0x13 & 0x1f),
        "spsr_abt": PSR_REGISTERS_FIRST + (0x17 & 0x1f),
        "spsr_irq": PSR_REGISTERS_FIRST + (0x12 & 0x1f),
        "spsr_und": PSR_REGISTERS_FIRST + (0x1b & 0x1f),
        "spsr_mon": PSR_REGISTERS_FIRST + (0x16 & 0x1f),
        "spsr_hyp": PSR_REGISTERS_FIRST + (0x1a & 0x1f),
    }
    
    # CP15 Registers (32-bit and 64-bit, all variants)
    # Formula 32-bit: base | ((cp_num & 0xf) << 16) | ((op1 & 0xf) << 12) | ((CRn & 0xf) << 8) | ((CRm & 0xf) << 4) | (op2 & 0xf)
    # Formula 64-bit: base | ((cp_num & 0xf) << 16) | ((op1 & 0xf) << 12) | ((CRm & 0xf) << 4)
    CP_REGISTERS = {
        "midr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "mpidr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x5 & 0xf),
        "id_pfr0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "id_pfr1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "id_dfr0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x2 & 0xf),
        "id_afr0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x3 & 0xf),
        "id_mmfr0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x4 & 0xf),
        "id_mmfr1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x5 & 0xf),
        "id_mmfr2": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x6 & 0xf),
        "id_mmfr3": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x7 & 0xf),
        "dacr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x3 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "contextidr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xd & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "sctlr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "actlr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "ttbcr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "ttbr0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "ttbr1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "ttbr0_64": CP_REGISTERS_64_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x2 & 0xf) << 4),
        "ttbr1_64": CP_REGISTERS_64_FIRST | ((0xf & 0xf) << 16) | ((0x1 & 0xf) << 12) | ((0x2 & 0xf) << 4),
        "hcr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "vtcr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x2 & 0xf),
        "vttbr_64": CP_REGISTERS_64_FIRST | ((0xf & 0xf) << 16) | ((0x6 & 0xf) << 12) | ((0x2 & 0xf) << 4),
        "scr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "nsacr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x2 & 0xf),
        "mvbar": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xc & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "sder": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "sctlr_ns": CP_NS_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "ttbcr_ns": CP_NS_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "ttbr0_ns": CP_NS_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "ttbr1_ns": CP_NS_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "ttbr0_64_ns": CP_NS_REGISTERS_64_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x2 & 0xf) << 4),
        "ttbr1_64_ns": CP_NS_REGISTERS_64_FIRST | ((0xf & 0xf) << 16) | ((0x1 & 0xf) << 12) | ((0x2 & 0xf) << 4),
        "scr_ns": CP_NS_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "nsacr_ns": CP_NS_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x2 & 0xf),
        "mvbar_ns": CP_NS_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xc & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "sder_ns": CP_NS_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "amair0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x0 & 0xf),
        "amair1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x1 & 0xf),
        "mair0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x0 & 0xf),
        "mair1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x1 & 0xf),
        "nmrr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "prrr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "cpacr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "mpuir": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x4 & 0xf),
        "ctr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "ccsidr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x1 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "clidr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x1 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "csselr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x2 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "fpscr": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "fpexc": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x8 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "fpsid": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "mvfr0": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x7 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "mvfr1": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "vpidr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "vmpidr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x5 & 0xf),
        "hsctlr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "hactlr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "hcr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "hdcr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "hcptr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x2 & 0xf),
        "hstr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x3 & 0xf),
        "hacr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x7 & 0xf),
        "htcr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "vtcr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x2 & 0xf),
        "httbr_hyp": CP_HYP_REGISTERS_64_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x2 & 0xf) << 4),
        "vttbr_hyp": CP_HYP_REGISTERS_64_FIRST | ((0xf & 0xf) << 16) | ((0x6 & 0xf) << 12) | ((0x2 & 0xf) << 4),
        "hadfsr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "haifsr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "hsr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x0 & 0xf),
        "hpfar_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x4 & 0xf),
        "hmair0_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x0 & 0xf),
        "hmair1_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x1 & 0xf),
        "hamair0_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x0 & 0xf),
        "hamair1_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x1 & 0xf),
        "hvbar_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xc & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "htpidr_hyp": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xd & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "cntvoff_hyp": CP_HYP_REGISTERS_64_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xe & 0xf) << 4),
    }
    
    # Debug Registers
    # Formula: debug_registers_first + (x & 0x3ff)
    DEBUG_REGISTERS = {
        "didr": DEBUG_REGISTERS_FIRST + (0 & 0x3ff),
        "dbgvcr": DEBUG_REGISTERS_FIRST + (7 & 0x3ff),
        "dbgecr": DEBUG_REGISTERS_FIRST + (9 & 0x3ff),
        "dbgdsccr": DEBUG_REGISTERS_FIRST + (10 & 0x3ff),
        "dbgdsmcr": DEBUG_REGISTERS_FIRST + (11 & 0x3ff),
        "dbgdscr": DEBUG_REGISTERS_FIRST + (34 & 0x3ff),
        "dbgdrcr": DEBUG_REGISTERS_FIRST + (36 & 0x3ff),
        "dbgpcsr": DEBUG_REGISTERS_FIRST + (40 & 0x3ff),
        "dbgcidsr": DEBUG_REGISTERS_FIRST + (41 & 0x3ff),
        "dbgvidsr": DEBUG_REGISTERS_FIRST + (42 & 0x3ff),
        "dbgbvr0": DEBUG_REGISTERS_FIRST + (64 & 0x3ff),
        "dbgbcr0": DEBUG_REGISTERS_FIRST + (80 & 0x3ff),
        "dbgwvr0": DEBUG_REGISTERS_FIRST + (96 & 0x3ff),
        "dbgwcr0": DEBUG_REGISTERS_FIRST + (112 & 0x3ff),
        "dbgoslar": DEBUG_REGISTERS_FIRST + (192 & 0x3ff),
        "dbgoslsr": DEBUG_REGISTERS_FIRST + (193 & 0x3ff),
        "dbgossrr": DEBUG_REGISTERS_FIRST + (194 & 0x3ff),
        "dbgosdlr": DEBUG_REGISTERS_FIRST + (195 & 0x3ff),
        "dbgprsr": DEBUG_REGISTERS_FIRST + (197 & 0x3ff),
        "dbgclaimset": DEBUG_REGISTERS_FIRST + (1000 & 0x3ff),
        "dbgclaimclr": DEBUG_REGISTERS_FIRST + (1001 & 0x3ff),
        "dbglar": DEBUG_REGISTERS_FIRST + (1004 & 0x3ff),
        "dbglsr": DEBUG_REGISTERS_FIRST + (1005 & 0x3ff),
        "dbgauthstatus": DEBUG_REGISTERS_FIRST + (1006 & 0x3ff),
        "dbgdevid1": DEBUG_REGISTERS_FIRST + (1009 & 0x3ff),
        "dbgdevid": DEBUG_REGISTERS_FIRST + (1010 & 0x3ff),
        "dbgdevtype": DEBUG_REGISTERS_FIRST + (1011 & 0x3ff),
    }
    
    # VFP Registers
    # Formula: vfp_registers_first + (reg & 0x1f)
    VFP_REGISTERS = {
        "fp0": VFP_REGISTERS_FIRST + (0 & 0x1f),
        "fp1": VFP_REGISTERS_FIRST + (1 & 0x1f),
        "fp2": VFP_REGISTERS_FIRST + (2 & 0x1f),
        "fp3": VFP_REGISTERS_FIRST + (3 & 0x1f),
        "fp4": VFP_REGISTERS_FIRST + (4 & 0x1f),
        "fp5": VFP_REGISTERS_FIRST + (5 & 0x1f),
        "fp6": VFP_REGISTERS_FIRST + (6 & 0x1f),
        "fp7": VFP_REGISTERS_FIRST + (7 & 0x1f),
        "fp8": VFP_REGISTERS_FIRST + (8 & 0x1f),
        "fp9": VFP_REGISTERS_FIRST + (9 & 0x1f),
        "fp10": VFP_REGISTERS_FIRST + (10 & 0x1f),
        "fp11": VFP_REGISTERS_FIRST + (11 & 0x1f),
        "fp12": VFP_REGISTERS_FIRST + (12 & 0x1f),
        "fp13": VFP_REGISTERS_FIRST + (13 & 0x1f),
        "fp14": VFP_REGISTERS_FIRST + (14 & 0x1f),
        "fp15": VFP_REGISTERS_FIRST + (15 & 0x1f),
        "fp16": VFP_REGISTERS_FIRST + (16 & 0x1f),
        "fp17": VFP_REGISTERS_FIRST + (17 & 0x1f),
        "fp18": VFP_REGISTERS_FIRST + (18 & 0x1f),
        "fp19": VFP_REGISTERS_FIRST + (19 & 0x1f),
        "fp20": VFP_REGISTERS_FIRST + (20 & 0x1f),
        "fp21": VFP_REGISTERS_FIRST + (21 & 0x1f),
        "fp22": VFP_REGISTERS_FIRST + (22 & 0x1f),
        "fp23": VFP_REGISTERS_FIRST + (23 & 0x1f),
        "fp24": VFP_REGISTERS_FIRST + (24 & 0x1f),
        "fp25": VFP_REGISTERS_FIRST + (25 & 0x1f),
        "fp26": VFP_REGISTERS_FIRST + (26 & 0x1f),
        "fp27": VFP_REGISTERS_FIRST + (27 & 0x1f),
        "fp28": VFP_REGISTERS_FIRST + (28 & 0x1f),
        "fp29": VFP_REGISTERS_FIRST + (29 & 0x1f),
        "fp30": VFP_REGISTERS_FIRST + (30 & 0x1f),
        "fp31": VFP_REGISTERS_FIRST + (31 & 0x1f),
    }
    
    # Register Aliases
    ALIASES = {
        "cr": "sctlr",
        "vcr": "dbgvcr",
        "dsccr": "dbgdsccr",
        "ttb0r": "ttbr0",
        "dscr": "dbgdscr",
        "bcr0": "dbgbcr0",
        "bvr0": "dbgbvr0",
        "wcr0": "dbgwcr0",
        "wvr0": "dbgwvr0",
        "elr_hyp": "r14_hyp",
    }
    
    def __init__(self):
        """Initialize the Cortex register manager"""
        self.all_registers = {}
        self.all_registers.update(self.CORE_REGISTERS)
        self.all_registers.update(self.PSR_REGISTERS)
        self.all_registers.update(self.CP_REGISTERS)
        self.all_registers.update(self.DEBUG_REGISTERS)
        self.all_registers.update(self.VFP_REGISTERS)
    
    def get_address_by_name(self, name):
        """Get register address by name"""
        name_lower = name.lower()
        
        # Check aliases first
        if name_lower in self.ALIASES:
            name_lower = self.ALIASES[name_lower]
        
        if name_lower in self.all_registers:
            return self.all_registers[name_lower]
        return None
    
    def get_core_reg(self, name):
        """Get core register address by name"""
        name_lower = name.lower()
        if name_lower in self.CORE_REGISTERS:
            return self.CORE_REGISTERS[name_lower]
        return None
    
    def get_psr_reg(self, name):
        """Get PSR register address by name"""
        name_lower = name.lower()
        if name_lower in self.PSR_REGISTERS:
            return self.PSR_REGISTERS[name_lower]
        return None
    
    def get_cp_reg(self, name):
        """Get CP15 register address by name"""
        name_lower = name.lower()
        if name_lower in self.CP_REGISTERS:
            return self.CP_REGISTERS[name_lower]
        return None
    
    def get_debug_reg(self, name):
        """Get debug register address by name"""
        name_lower = name.lower()
        if name_lower in self.DEBUG_REGISTERS:
            return self.DEBUG_REGISTERS[name_lower]
        return None
    
    def get_vfp_reg(self, name):
        """Get VFP register address by name"""
        name_lower = name.lower()
        if name_lower in self.VFP_REGISTERS:
            return self.VFP_REGISTERS[name_lower]
        return None
    
    def is_core_reg(self, name):
        """Check if register is a core register"""
        return name.lower() in self.CORE_REGISTERS
    
    def is_psr_reg(self, name):
        """Check if register is a PSR register"""
        return name.lower() in self.PSR_REGISTERS
    
    def is_cp_reg(self, name):
        """Check if register is a CP15 register"""
        return name.lower() in self.CP_REGISTERS
    
    def is_debug_reg(self, name):
        """Check if register is a debug register"""
        return name.lower() in self.DEBUG_REGISTERS
    
    def is_vfp_reg(self, name):
        """Check if register is a VFP register"""
        return name.lower() in self.VFP_REGISTERS
