# -*- coding: utf-8 -*-
"""
 Copyright 2025 NXP

 NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be
 used strictly in accordance with the applicable license terms. By expressly
 accepting such terms or by downloading, installing, activating and/or otherwise
 using the software, you are agreeing that you have read, and that you agree to
 comply with and are bound by, such license terms. If you do not agree to be
 bound by the applicable license terms, then you may not retain, install,
 activate or otherwise use the software.

"""

class CortexMRegisters:
    """
    Cortex-M microcontroller register definitions
    """
    
    # Base addresses from TCL file
    DEBUG_REGISTERS_FIRST = 0x1000
    CORE_REGISTERS_FIRST = 0x2000
    
    # Debug Registers Map
    # Formula: debug_registers_first + (x & 0xfff)
    DEBUG_REGISTERS = {
        "dhcsr": DEBUG_REGISTERS_FIRST + (892 & 0xfff),  # 0x137C
        "dcrsr": DEBUG_REGISTERS_FIRST + (893 & 0xfff),  # 0x137D
        "dcrdr": DEBUG_REGISTERS_FIRST + (894 & 0xfff),  # 0x137E
        "demcr": DEBUG_REGISTERS_FIRST + (895 & 0xfff),  # 0x137F
    }
    
    # Core Registers Map
    # Formula: core_registers_first + (reg & 0xff)
    CORE_REGISTERS = {
        "r0": CORE_REGISTERS_FIRST + (0 & 0xff),
        "r1": CORE_REGISTERS_FIRST + (1 & 0xff),
        "r2": CORE_REGISTERS_FIRST + (2 & 0xff),
        "r3": CORE_REGISTERS_FIRST + (3 & 0xff),
        "r4": CORE_REGISTERS_FIRST + (4 & 0xff),
        "r5": CORE_REGISTERS_FIRST + (5 & 0xff),
        "r6": CORE_REGISTERS_FIRST + (6 & 0xff),
        "r7": CORE_REGISTERS_FIRST + (7 & 0xff),
        "r8": CORE_REGISTERS_FIRST + (8 & 0xff),
        "r9": CORE_REGISTERS_FIRST + (9 & 0xff),
        "r10": CORE_REGISTERS_FIRST + (10 & 0xff),
        "r11": CORE_REGISTERS_FIRST + (11 & 0xff),
        "r12": CORE_REGISTERS_FIRST + (12 & 0xff),
        "r13": CORE_REGISTERS_FIRST + (13 & 0xff),
        "r14": CORE_REGISTERS_FIRST + (14 & 0xff),
        "r15": CORE_REGISTERS_FIRST + (15 & 0xff),
        "sp": CORE_REGISTERS_FIRST + (13 & 0xff),
        "lr": CORE_REGISTERS_FIRST + (14 & 0xff),
        "pc": CORE_REGISTERS_FIRST + (15 & 0xff),
        "xpsr": CORE_REGISTERS_FIRST + (16 & 0xff),
        "msp": CORE_REGISTERS_FIRST + (17 & 0xff),
        "psp": CORE_REGISTERS_FIRST + (18 & 0xff),
        "control": CORE_REGISTERS_FIRST + (20 & 0xff),
        "faultmask": CORE_REGISTERS_FIRST + (20 & 0xff),
        "basepri": CORE_REGISTERS_FIRST + (20 & 0xff),
        "primask": CORE_REGISTERS_FIRST + (20 & 0xff),
        "fpscr": CORE_REGISTERS_FIRST + (33 & 0xff),
        "s0": CORE_REGISTERS_FIRST + (64 & 0xff),
        "s1": CORE_REGISTERS_FIRST + (65 & 0xff),
        "s2": CORE_REGISTERS_FIRST + (66 & 0xff),
        "s3": CORE_REGISTERS_FIRST + (67 & 0xff),
        "s4": CORE_REGISTERS_FIRST + (68 & 0xff),
        "s5": CORE_REGISTERS_FIRST + (69 & 0xff),
        "s6": CORE_REGISTERS_FIRST + (70 & 0xff),
        "s7": CORE_REGISTERS_FIRST + (71 & 0xff),
        "s8": CORE_REGISTERS_FIRST + (72 & 0xff),
        "s9": CORE_REGISTERS_FIRST + (73 & 0xff),
        "s10": CORE_REGISTERS_FIRST + (74 & 0xff),
        "s11": CORE_REGISTERS_FIRST + (75 & 0xff),
        "s12": CORE_REGISTERS_FIRST + (76 & 0xff),
        "s13": CORE_REGISTERS_FIRST + (77 & 0xff),
        "s14": CORE_REGISTERS_FIRST + (78 & 0xff),
        "s15": CORE_REGISTERS_FIRST + (79 & 0xff),
        "s16": CORE_REGISTERS_FIRST + (80 & 0xff),
        "s17": CORE_REGISTERS_FIRST + (81 & 0xff),
        "s18": CORE_REGISTERS_FIRST + (82 & 0xff),
        "s19": CORE_REGISTERS_FIRST + (83 & 0xff),
        "s20": CORE_REGISTERS_FIRST + (84 & 0xff),
        "s21": CORE_REGISTERS_FIRST + (85 & 0xff),
        "s22": CORE_REGISTERS_FIRST + (86 & 0xff),
        "s23": CORE_REGISTERS_FIRST + (87 & 0xff),
        "s24": CORE_REGISTERS_FIRST + (88 & 0xff),
        "s25": CORE_REGISTERS_FIRST + (89 & 0xff),
        "s26": CORE_REGISTERS_FIRST + (90 & 0xff),
        "s27": CORE_REGISTERS_FIRST + (91 & 0xff),
        "s28": CORE_REGISTERS_FIRST + (92 & 0xff),
        "s29": CORE_REGISTERS_FIRST + (93 & 0xff),
        "s30": CORE_REGISTERS_FIRST + (94 & 0xff),
        "s31": CORE_REGISTERS_FIRST + (95 & 0xff),
    }
    
    def __init__(self):
        """Initialize the Cortex-M register manager"""
        self.all_registers = {}
        self.all_registers.update(self.CORE_REGISTERS)
        self.all_registers.update(self.DEBUG_REGISTERS)
    
    def get_address_by_name(self, name):
        """Get register address by name"""
        name_lower = name.lower()
        if name_lower in self.all_registers:
            return self.all_registers[name_lower]
        return None
    
    def get_core_reg(self, name):
        """Get core register address by name"""
        name_lower = name.lower()
        if name_lower in self.CORE_REGISTERS:
            return self.CORE_REGISTERS[name_lower]
        return None
    
    def get_debug_reg(self, name):
        """Get debug register address by name"""
        name_lower = name.lower()
        if name_lower in self.DEBUG_REGISTERS:
            return self.DEBUG_REGISTERS[name_lower]
        return None
    
    def is_core_reg(self, name):
        """Check if register is a core register"""
        return name.lower() in self.CORE_REGISTERS
    
    def is_debug_reg(self, name):
        """Check if register is a debug register"""
        return name.lower() in self.DEBUG_REGISTERS