Read ARMv8-A core L1 Cache contents.
    usage: cache_read type [-c/-context] \" \" [-s/-set] 0 [-w/-way] 0 [-b/-begin] 0 [-e/-end] 0
        type            -   i/icache or d/dcache
        [-c/-context]   -   GTA (GDB server) debug context :ccs:<soc>[:core]
                            If present, the context can be a core context;
                            if not, the current context is used.
                            e.g. ":ccs:S32G2XX:CortexA53#0"
        [-s/-set]       -   The Cache set index where the Cache Line will be read. 
                            [0..255] in case of icache
                            [0..127] in case of dcache
        [-w/-way]       -   The Cache way to read where the Cache Line will be read.
                            [0..1] in case of icache
                            [0..3] in case of dcache
        [-b/-begin]     -   The begining set where we start our read. Must be smaller
                            than the ending set. Must not be used in conjunction with
                            set or way parameters.
        [-e/-end]       -   The end set where we end our read. Must be larger
                            than the starting set. Must not be used in conjunction 
                            with set or way parameters.
        
                                                                  
        E.g.: cache_read -c :ccs:S32G2XX:CortexA53#0 -s 2 -w 3 dcache
                                                                      Selected WAY 3        
                                                                            |    
                                                                            v
                                                                    #################
                          WAY 0           WAY 1           WAY 2     #     WAY 3     #  
                                                                    #               #  
            Index       Tag Data        Tag Data        Tag Data    #   Tag Data    #  
                        ---------       ---------       ---------   #   ---------   #   
            0           |   |   |       |   |   |       |   |   |   #   |   |   |   #   
            1           |   |   |       |   |   |       |   |   |   #   |   |   |   #   
        ###############################################################################
        #   2           |   |   |       |   |   |       |   |   |   #   |123|456|   # #   <-- Selected SET 2  
        ###############################################################################
            3           |   |   |       |   |   |       |   |   |   #   |   |   |   #   
            ...         |   |   |       |   |   |       |   |   |   #   |   |   |   #   
            254         |   |   |       |   |   |       |   |   |   #   |   |   |   #   
            255         |   |   |       |   |   |       |   |   |   #   |   |   |   #   
                        ---------       ---------       ---------   #   ---------   #   
                                                                    #################
                        
        In the exampe above we slected from the dcache set 2 and way 3 to read the Cache Line containing the TAG 123 and DATA 456.

        Every register and bit shift, that is not explained in comments, for cache read operation, can be found in the Cortex A53 TRM (Technical Reference Manual).

        Other valid examples:
            cache_read -c :ccs:S32G2XX:CortexA53#0 -s 0 -w 0 dcache
            cache_read icache -s 0 -c :ccs:S32G2XX:CortexA53#0 -w 0 
            cache_read -b 0 -e 100 dcache
            cache_read -b 0 -e 100 icache
            cache_read -s 0 -w 0 icache
            cache_read -c :ccs:S32G2XX:CortexA53#0 dcache
            cache_read -c :ccs:S32G2XX:CortexA53#0 icache
            cache_read dcache
            cache_read icache
            etc.