# -*- coding: utf-8 -*-
"""
 Copyright 2025 NXP

 NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be
 used strictly in accordance with the applicable license terms. By expressly
 accepting such terms or by downloading, installing, activating and/or otherwise
 using the software, you are agreeing that you have read, and that you agree to
 comply with and are bound by, such license terms. If you do not agree to be
 bound by the applicable license terms, then you may not retain, install,
 activate or otherwise use the software.

"""

class ARMv8RNRegisters:
    """
    ARMv8-R Cortex-R82 processor register definitions
    """
    
    # Base addresses from TCL file
    DEBUG_REGISTERS_FIRST = 0x1000
    CORE_REGISTERS_FIRST = 0x2000
    PSR_REGISTERS_FIRST = 0x3000
    VFP_REGISTERS_FIRST = 0x4000
    A64_CORE_REGISTERS_FIRST = 0x5000
    MISC_REGISTERS_FIRST = 0x6000
    SYSTEM_REGISTERS_FIRST = 0x10000
    CP_REGISTERS_FIRST = 0x100000
    CP_REGISTERS_64_FIRST = 0x200000
    CP_NS_REGISTERS_FIRST = 0x300000
    CP_NS_REGISTERS_64_FIRST = 0x400000
    CP_HYP_REGISTERS_FIRST = 0x500000
    CP_HYP_REGISTERS_64_FIRST = 0x600000
    
    # Core Registers
    # Formula: core_registers_first + ((mode & 0x1f) << 4) + (reg & 0xf)
    CORE_REGISTERS = {
        # usr/sys mode (0x1f) - usr and sys generally are same
        "r0": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (0 & 0xf),
        "r1": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (1 & 0xf),
        "r2": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (2 & 0xf),
        "r3": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (3 & 0xf),
        "r4": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (4 & 0xf),
        "r5": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (5 & 0xf),
        "r6": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (6 & 0xf),
        "r7": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (7 & 0xf),
        "r8": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (8 & 0xf),
        "r9": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (9 & 0xf),
        "r10": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (10 & 0xf),
        "r11": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (11 & 0xf),
        "r12": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (12 & 0xf),
        "r13": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (13 & 0xf),
        "r14": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (14 & 0xf),
        "r15": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (15 & 0xf),
        
        # Banked sys mode registers
        "r8_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (8 & 0xf),
        "r9_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (9 & 0xf),
        "r10_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (10 & 0xf),
        "r11_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (11 & 0xf),
        "r12_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (12 & 0xf),
        "r13_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (13 & 0xf),
        "r14_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (14 & 0xf),
        "r15_sys": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (15 & 0xf),
        
        # fiq mode (0x11)
        "r8_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (8 & 0xf),
        "r9_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (9 & 0xf),
        "r10_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (10 & 0xf),
        "r11_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (11 & 0xf),
        "r12_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (12 & 0xf),
        "r13_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (13 & 0xf),
        "r14_fiq": CORE_REGISTERS_FIRST + ((0x11 & 0x1f) << 4) + (14 & 0xf),
        
        # svc mode (0x13)
        "r13_svc": CORE_REGISTERS_FIRST + ((0x13 & 0x1f) << 4) + (13 & 0xf),
        "r14_svc": CORE_REGISTERS_FIRST + ((0x13 & 0x1f) << 4) + (14 & 0xf),
        
        # abt mode (0x17)
        "r13_abt": CORE_REGISTERS_FIRST + ((0x17 & 0x1f) << 4) + (13 & 0xf),
        "r14_abt": CORE_REGISTERS_FIRST + ((0x17 & 0x1f) << 4) + (14 & 0xf),
        
        # irq mode (0x12)
        "r13_irq": CORE_REGISTERS_FIRST + ((0x12 & 0x1f) << 4) + (13 & 0xf),
        "r14_irq": CORE_REGISTERS_FIRST + ((0x12 & 0x1f) << 4) + (14 & 0xf),
        
        # und mode (0x1b)
        "r13_und": CORE_REGISTERS_FIRST + ((0x1b & 0x1f) << 4) + (13 & 0xf),
        "r14_und": CORE_REGISTERS_FIRST + ((0x1b & 0x1f) << 4) + (14 & 0xf),
        
        # hyp mode (0x1a)
        "r13_hyp": CORE_REGISTERS_FIRST + ((0x1a & 0x1f) << 4) + (13 & 0xf),
        "elr_hyp": CORE_REGISTERS_FIRST + ((0x1a & 0x1f) << 4) + (14 & 0xf),
        
        # pc as core register
        "pc": CORE_REGISTERS_FIRST + ((0x1f & 0x1f) << 4) + (15 & 0xf),
    }
    
    # Program Status Registers
    # Formula: psr_registers_first + (mode & 0x1f)
    PSR_REGISTERS = {
        "cpsr": PSR_REGISTERS_FIRST + (0x1f & 0x1f),
        "spsr_fiq": PSR_REGISTERS_FIRST + (0x11 & 0x1f),
        "spsr_svc": PSR_REGISTERS_FIRST + (0x13 & 0x1f),
        "spsr_abt": PSR_REGISTERS_FIRST + (0x17 & 0x1f),
        "spsr_irq": PSR_REGISTERS_FIRST + (0x12 & 0x1f),
        "spsr_und": PSR_REGISTERS_FIRST + (0x1b & 0x1f),
        "spsr_hyp": PSR_REGISTERS_FIRST + (0x1a & 0x1f),
    }
    
    # R-profile subset of AArch32 32-bit registers implemented in HYP
    # Formula: cp_hyp_registers_first | ((cp_num & 0xf) << 16) | ((op1 & 0xf) << 12) | ((CRn & 0xf) << 8) | ((CRm & 0xf) << 4) | (op2 & 0xf)
    CP_HYP_REGISTERS = {
        # fixed op1:=4; Formatted as {cp_num op1 CRn CRm op2}
        "vpidr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "vmpidr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x5 & 0xf),
        
        "hsctlr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "hactlr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "hactlr2": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x3 & 0xf),
        
        "hcr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "hdcr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "hcptr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x2 & 0xf),
        "hstr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x3 & 0xf),
        "hcr2": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x4 & 0xf),
        "hacr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x7 & 0xf),
        
        "hadfsr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "haifsr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "hsr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x0 & 0xf),
        
        "hdfar": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "hifar": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "hpfar": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x4 & 0xf),
        
        # WO
        "ats1hr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x7 & 0xf) << 8) | ((0x8 & 0xf) << 4) | (0x0 & 0xf),
        "ats1hw": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x7 & 0xf) << 8) | ((0x8 & 0xf) << 4) | (0x1 & 0xf),
        
        "hmair0": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x0 & 0xf),
        "hmair1": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x1 & 0xf),
        "hamair0": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x0 & 0xf),
        "hamair1": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x1 & 0xf),
        "hvbar": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xc & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "hrmr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xc & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "htpidr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xd & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        
        # new in R-profile
        "hmpuir": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x4 & 0xf),
        "hprbar": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x0 & 0xf),
        "hprenr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "hprlar": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x1 & 0xf),
        "hprselr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x1 & 0xf),
        "vsctlr": CP_HYP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
    }
    
    # R-profile subset of AArch32 64-bit registers
    # Formula: cp_hyp_registers_64_first | ((cp_num & 0xf) << 16) | ((op1 & 0xf) << 12) | ((CRm & 0xf) << 4)
    CP_HYP_REGISTERS_64 = {
        "cntvoff": CP_HYP_REGISTERS_64_FIRST | ((0xf & 0xf) << 16) | ((0x4 & 0xf) << 12) | ((0xe & 0xf) << 4),
    }
    
    # Debug Registers - memory mapped
    # Formula: debug_registers_first + (x & 0x3ff)
    DEBUG_REGISTERS = {
        "edesr": DEBUG_REGISTERS_FIRST + ((0x020 // 4) & 0x3ff),
        "edecr": DEBUG_REGISTERS_FIRST + ((0x024 // 4) & 0x3ff),
        "edwar": DEBUG_REGISTERS_FIRST + ((0x030 // 4) & 0x3ff),
        "edwarhi": DEBUG_REGISTERS_FIRST + ((0x034 // 4) & 0x3ff),
        "dbgdtrrx_el0": DEBUG_REGISTERS_FIRST + ((0x080 // 4) & 0x3ff),
        "editr": DEBUG_REGISTERS_FIRST + ((0x084 // 4) & 0x3ff),
        "edscr": DEBUG_REGISTERS_FIRST + ((0x088 // 4) & 0x3ff),
        "dbgdtrtx_el0": DEBUG_REGISTERS_FIRST + ((0x08c // 4) & 0x3ff),
        "edrcr": DEBUG_REGISTERS_FIRST + ((0x090 // 4) & 0x3ff),
        "edacr": DEBUG_REGISTERS_FIRST + ((0x094 // 4) & 0x3ff),
        "edeccr": DEBUG_REGISTERS_FIRST + ((0x098 // 4) & 0x3ff),
        "edpcsr": DEBUG_REGISTERS_FIRST + ((0x0a0 // 4) & 0x3ff),
        "edcidsr": DEBUG_REGISTERS_FIRST + ((0x0a4 // 4) & 0x3ff),
        "edvidsr": DEBUG_REGISTERS_FIRST + ((0x0a8 // 4) & 0x3ff),
        
        "oslar": DEBUG_REGISTERS_FIRST + ((0x0300 // 4) & 0x3ff),
        "edprcr": DEBUG_REGISTERS_FIRST + ((0x0310 // 4) & 0x3ff),
        "edprsr": DEBUG_REGISTERS_FIRST + ((0x0314 // 4) & 0x3ff),
        
        "midr": DEBUG_REGISTERS_FIRST + ((0xd00 // 4) & 0x3ff),
        "edpfr_lo": DEBUG_REGISTERS_FIRST + ((0xd20 // 4) & 0x3ff),
        "edpfr_hi": DEBUG_REGISTERS_FIRST + ((0xd24 // 4) & 0x3ff),
        "eddfr_lo": DEBUG_REGISTERS_FIRST + ((0xd28 // 4) & 0x3ff),
        "eddfr_hi": DEBUG_REGISTERS_FIRST + ((0xd2c // 4) & 0x3ff),
        
        "editctrl": DEBUG_REGISTERS_FIRST + ((0xf00 // 4) & 0x3ff),
        "dbgclaimset_el1": DEBUG_REGISTERS_FIRST + ((0xfa0 // 4) & 0x3ff),
        "dbgclaimclr_el1": DEBUG_REGISTERS_FIRST + ((0xfa4 // 4) & 0x3ff),
        "eddevaff0": DEBUG_REGISTERS_FIRST + ((0xfa8 // 4) & 0x3ff),
        "eddevaff1": DEBUG_REGISTERS_FIRST + ((0xfac // 4) & 0x3ff),
        "edlar": DEBUG_REGISTERS_FIRST + ((0xfb0 // 4) & 0x3ff),
        "edlsr": DEBUG_REGISTERS_FIRST + ((0xfb4 // 4) & 0x3ff),
        "dbgauthstatus_el1": DEBUG_REGISTERS_FIRST + ((0xfb8 // 4) & 0x3ff),
        "eddevarch": DEBUG_REGISTERS_FIRST + ((0xfbc // 4) & 0x3ff),
        "eddevid2": DEBUG_REGISTERS_FIRST + ((0xfc0 // 4) & 0x3ff),
        "eddevid1": DEBUG_REGISTERS_FIRST + ((0xfc4 // 4) & 0x3ff),
        "eddevid": DEBUG_REGISTERS_FIRST + ((0xfc8 // 4) & 0x3ff),
        "eddevtype": DEBUG_REGISTERS_FIRST + ((0xfcc // 4) & 0x3ff),
        "edpidr4": DEBUG_REGISTERS_FIRST + ((0xfd0 // 4) & 0x3ff),
        "edpidr0": DEBUG_REGISTERS_FIRST + ((0xfe0 // 4) & 0x3ff),
        "edpidr1": DEBUG_REGISTERS_FIRST + ((0xfe4 // 4) & 0x3ff),
        "edpidr2": DEBUG_REGISTERS_FIRST + ((0xfe8 // 4) & 0x3ff),
        "edpidr3": DEBUG_REGISTERS_FIRST + ((0xfec // 4) & 0x3ff),
        "edcidr0": DEBUG_REGISTERS_FIRST + ((0xff0 // 4) & 0x3ff),
        "edcidr1": DEBUG_REGISTERS_FIRST + ((0xff4 // 4) & 0x3ff),
        "edcidr2": DEBUG_REGISTERS_FIRST + ((0xff8 // 4) & 0x3ff),
        "edcidr3": DEBUG_REGISTERS_FIRST + ((0xffc // 4) & 0x3ff),
    }
    
    # Debug Breakpoint and Watchpoint registers (generated in loop)
    for n in range(8):
        DEBUG_REGISTERS.update({
            "dbgbvr{}".format(n): DEBUG_REGISTERS_FIRST + (((0x400 + 16 * n) // 4) & 0x3ff),
            "dbgbcr{}".format(n): DEBUG_REGISTERS_FIRST + (((0x408 + 16 * n) // 4) & 0x3ff),
            "dbgwvr{}".format(n): DEBUG_REGISTERS_FIRST + (((0x800 + 16 * n) // 4) & 0x3ff),
            "dbgwcr{}".format(n): DEBUG_REGISTERS_FIRST + (((0x808 + 16 * n) // 4) & 0x3ff),
        })
    
    # Debug Registers - CP15
    # Formula: cp_registers_first | ((cp_num & 0xf) << 16) | ((op1 & 0xf) << 12) | ((CRn & 0xf) << 8) | ((CRm & 0xf) << 4) | (op2 & 0xf)
    DEBUG_CP15_REGISTERS = {
        "dbgdidr": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "dbgdtrrxext": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "jidr": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "dbgdscrint": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "dbgdcccint": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x0 & 0xf),
        "dbgdscrext": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x2 & 0xf),
        "dbgdtrtxext": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x3 & 0xf),
        "dbgwfar": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x6 & 0xf) << 4) | (0x0 & 0xf),
        "dbgvcr": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x7 & 0xf) << 4) | (0x0 & 0xf),
        "dbgdrar": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "joscr": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "dbgoslsr": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x4 & 0xf),
        "dbgosdlr": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x4 & 0xf),
        "dbgdsar": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x2 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "dbgdevid2": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x7 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x7 & 0xf),
        "dbgdevid1": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x7 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x7 & 0xf),
        "dbgdevid": CP_REGISTERS_FIRST | ((0xe & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x7 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x7 & 0xf),
    }
    
    # ARMv8-R CP15 Registers
    # Formula: cp_registers_first | ((cp_num & 0xf) << 16) | ((op1 & 0xf) << 12) | ((CRn & 0xf) << 8) | ((CRm & 0xf) << 4) | (op2 & 0xf)
    CP_REGISTERS = {
        # CRn = c0
        "midr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "ctr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "tcmtr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "tlbtr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x3 & 0xf),
        "mpuir": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x4 & 0xf),
        "mpidr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x5 & 0xf),
        "revidr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x6 & 0xf),
        
        "id_pfr0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "id_pfr1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "id_dfr0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x2 & 0xf),
        "id_afr0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x3 & 0xf),
        "id_mmfr0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x4 & 0xf),
        "id_mmfr1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x5 & 0xf),
        "id_mmfr2": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x6 & 0xf),
        "id_mmfr3": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x7 & 0xf),
        
        "id_isar0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x0 & 0xf),
        "id_isar1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x1 & 0xf),
        "id_isar2": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x2 & 0xf),
        "id_isar3": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x3 & 0xf),
        "id_isar4": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x4 & 0xf),
        "id_isar5": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x5 & 0xf),
        "id_mmfr4": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x6 & 0xf),
        
        "ccsidr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x1 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "cldidr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x1 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "aidr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x1 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x7 & 0xf),
        "csselr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x2 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        
        # CRn = c1
        "sctlr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "actlr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "cpacr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "actlr2": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x3 & 0xf),
        "nsacr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x1 &        0xf) << 4) | (0x2 & 0xf),
        
        # CRn = c4
        "icc_pmr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x4 & 0xf) << 8) | ((0x6 & 0xf) << 4) | (0x0 & 0xf),
        "icv_pmr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x4 & 0xf) << 8) | ((0x6 & 0xf) << 4) | (0x0 & 0xf),
        "dspsr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x3 & 0xf) << 12) | ((0x4 & 0xf) << 8) | ((0x5 & 0xf) << 4) | (0x0 & 0xf),
        "dlr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x3 & 0xf) << 12) | ((0x4 & 0xf) << 8) | ((0x5 & 0xf) << 4) | (0x1 & 0xf),
        
        # CRn = c5
        "dfsr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "ifsr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x1 & 0xf),
        "adfsr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "aifsr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        
        # CRn = c6
        "dfar": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "ifar": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x2 & 0xf),
        "prselr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x1 & 0xf),
        "prbar": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x0 & 0xf),
        "prlar": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x1 & 0xf),
        "prbar0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x8 & 0xf) << 4) | (0x0 & 0xf),
        "prbar2": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x9 & 0xf) << 4) | (0x0 & 0xf),
        "prbar4": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xa & 0xf) << 4) | (0x0 & 0xf),
        "prbar6": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xb & 0xf) << 4) | (0x0 & 0xf),
        "prbar8": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xc & 0xf) << 4) | (0x0 & 0xf),
        "prbar10": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xd & 0xf) << 4) | (0x0 & 0xf),
        "prbar12": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xe & 0xf) << 4) | (0x0 & 0xf),
        "prbar14": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xf & 0xf) << 4) | (0x0 & 0xf),
        "prlar0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x8 & 0xf) << 4) | (0x1 & 0xf),
        "prlar2": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x9 & 0xf) << 4) | (0x1 & 0xf),
        "prlar4": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xa & 0xf) << 4) | (0x1 & 0xf),
        "prlar6": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xb & 0xf) << 4) | (0x1 & 0xf),
        "prlar8": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xc & 0xf) << 4) | (0x1 & 0xf),
        "prlar10": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xd & 0xf) << 4) | (0x1 & 0xf),
        "prlar12": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xe & 0xf) << 4) | (0x1 & 0xf),
        "prlar14": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xf & 0xf) << 4) | (0x1 & 0xf),
        "prbar1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x8 & 0xf) << 4) | (0x4 & 0xf),
        "prbar3": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x9 & 0xf) << 4) | (0x4 & 0xf),
        "prbar5": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xa & 0xf) << 4) | (0x4 & 0xf),
        "prbar7": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xb & 0xf) << 4) | (0x4 & 0xf),
        "prbar9": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xc & 0xf) << 4) | (0x4 & 0xf),
        "prbar11": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xd & 0xf) << 4) | (0x4 & 0xf),
        "prbar13": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xe & 0xf) << 4) | (0x4 & 0xf),
        "prbar15": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xf & 0xf) << 4) | (0x4 & 0xf),
        "prlar1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x8 & 0xf) << 4) | (0x5 & 0xf),
        "prlar3": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x9 & 0xf) << 4) | (0x5 & 0xf),
        "prlar5": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xa & 0xf) << 4) | (0x5 & 0xf),
        "prlar7": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xb & 0xf) << 4) | (0x5 & 0xf),
        "prlar9": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xc & 0xf) << 4) | (0x5 & 0xf),
        "prlar11": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xd & 0xf) << 4) | (0x5 & 0xf),
        "prlar13": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xe & 0xf) << 4) | (0x5 & 0xf),
        "prlar15": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0xf & 0xf) << 4) | (0x5 & 0xf),
        
        # CRn = c9
        "imp_atcmregionr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x9 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "imp_btcmregionr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x9 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "imp_ctcmregionr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0x9 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x2 & 0xf),
        "imp_csctlr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x1 & 0xf) << 12) | ((0x9 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x0 & 0xf),
        "imp_bpctlr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x1 & 0xf) << 12) | ((0x9 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x1 & 0xf),
        "imp_memprotctlr": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x1 & 0xf) << 12) | ((0x9 & 0xf) << 8) | ((0x1 & 0xf) << 4) | (0x2 & 0xf),
        
        # CRn = c10
        "mair0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x0 & 0xf),
        "mair1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x2 & 0xf) << 4) | (0x1 & 0xf),
        "amair0": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x0 & 0xf),
        "amair1": CP_REGISTERS_FIRST | ((0xf & 0xf) << 16) | ((0x0 & 0xf) << 12) | ((0xa & 0xf) << 8) | ((0x3 & 0xf) << 4) | (0x1 & 0xf),
    }
    
    # FPU Registers
    # Formula: cp_registers_first | ((cp_num & 0xf) << 16) | ((op1 & 0xf) << 12) | ((CRn & 0xf) << 8) | ((CRm & 0xf) << 4) | (op2 & 0xf)
    FPU_REGISTERS = {
        "fpscr": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x1 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "fpexc": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x8 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "fpsid": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x0 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "mvfr0": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x7 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "mvfr1": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x6 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
        "mvfr2": CP_REGISTERS_FIRST | ((0xa & 0xf) << 16) | ((0x7 & 0xf) << 12) | ((0x5 & 0xf) << 8) | ((0x0 & 0xf) << 4) | (0x0 & 0xf),
    }
    
    # VFP Registers
    # Formula: vfp_registers_first + (reg & 0x1f)
    VFP_REGISTERS = {
        "fp0": VFP_REGISTERS_FIRST + (0 & 0x1f),
        "fp1": VFP_REGISTERS_FIRST + (1 & 0x1f),
        "fp2": VFP_REGISTERS_FIRST + (2 & 0x1f),
        "fp3": VFP_REGISTERS_FIRST + (3 & 0x1f),
        "fp4": VFP_REGISTERS_FIRST + (4 & 0x1f),
        "fp5": VFP_REGISTERS_FIRST + (5 & 0x1f),
        "fp6": VFP_REGISTERS_FIRST + (6 & 0x1f),
        "fp7": VFP_REGISTERS_FIRST + (7 & 0x1f),
        "fp8": VFP_REGISTERS_FIRST + (8 & 0x1f),
        "fp9": VFP_REGISTERS_FIRST + (9 & 0x1f),
        "fp10": VFP_REGISTERS_FIRST + (10 & 0x1f),
        "fp11": VFP_REGISTERS_FIRST + (11 & 0x1f),
        "fp12": VFP_REGISTERS_FIRST + (12 & 0x1f),
        "fp13": VFP_REGISTERS_FIRST + (13 & 0x1f),
        "fp14": VFP_REGISTERS_FIRST + (14 & 0x1f),
        "fp15": VFP_REGISTERS_FIRST + (15 & 0x1f),
        "fp16": VFP_REGISTERS_FIRST + (16 & 0x1f),
        "fp17": VFP_REGISTERS_FIRST + (17 & 0x1f),
        "fp18": VFP_REGISTERS_FIRST + (18 & 0x1f),
        "fp19": VFP_REGISTERS_FIRST + (19 & 0x1f),
        "fp20": VFP_REGISTERS_FIRST + (20 & 0x1f),
        "fp21": VFP_REGISTERS_FIRST + (21 & 0x1f),
        "fp22": VFP_REGISTERS_FIRST + (22 & 0x1f),
        "fp23": VFP_REGISTERS_FIRST + (23 & 0x1f),
        "fp24": VFP_REGISTERS_FIRST + (24 & 0x1f),
        "fp25": VFP_REGISTERS_FIRST + (25 & 0x1f),
        "fp26": VFP_REGISTERS_FIRST + (26 & 0x1f),
        "fp27": VFP_REGISTERS_FIRST + (27 & 0x1f),
        "fp28": VFP_REGISTERS_FIRST + (28 & 0x1f),
        "fp29": VFP_REGISTERS_FIRST + (29 & 0x1f),
        "fp30": VFP_REGISTERS_FIRST + (30 & 0x1f),
        "fp31": VFP_REGISTERS_FIRST + (31 & 0x1f),
    }
    
    # Register Aliases (none in ARMv8-RN)
    ALIASES = {}
    
    def __init__(self):
        """Initialize the ARMv8-RN register manager"""
        self.all_registers = {}
        self.all_registers.update(self.CORE_REGISTERS)
        self.all_registers.update(self.PSR_REGISTERS)
        self.all_registers.update(self.CP_HYP_REGISTERS)
        self.all_registers.update(self.CP_HYP_REGISTERS_64)
        self.all_registers.update(self.DEBUG_REGISTERS)
        self.all_registers.update(self.DEBUG_CP15_REGISTERS)
        self.all_registers.update(self.CP_REGISTERS)
        self.all_registers.update(self.FPU_REGISTERS)
        self.all_registers.update(self.VFP_REGISTERS)
    
    def get_address_by_name(self, name):
        """Get register address by name"""
        name_lower = name.lower()
        
        # Check aliases first
        if name_lower in self.ALIASES:
            name_lower = self.ALIASES[name_lower]
        
        if name_lower in self.all_registers:
            return self.all_registers[name_lower]
        return None
    
    def get_core_reg(self, name):
        """Get core register address by name"""
        name_lower = name.lower()
        if name_lower in self.CORE_REGISTERS:
            return self.CORE_REGISTERS[name_lower]
        return None
    
    def get_psr_reg(self, name):
        """Get PSR register address by name"""
        name_lower = name.lower()
        if name_lower in self.PSR_REGISTERS:
            return self.PSR_REGISTERS[name_lower]
        return None
    
    def get_cp_hyp_reg(self, name):
        """Get CP HYP register address by name"""
        name_lower = name.lower()
        if name_lower in self.CP_HYP_REGISTERS:
            return self.CP_HYP_REGISTERS[name_lower]
        elif name_lower in self.CP_HYP_REGISTERS_64:
            return self.CP_HYP_REGISTERS_64[name_lower]
        return None
    
    def get_debug_reg(self, name):
        """Get debug register address by name"""
        name_lower = name.lower()
        if name_lower in self.DEBUG_REGISTERS:
            return self.DEBUG_REGISTERS[name_lower]
        elif name_lower in self.DEBUG_CP15_REGISTERS:
            return self.DEBUG_CP15_REGISTERS[name_lower]
        return None
    
    def get_cp_reg(self, name):
        """Get CP15 register address by name"""
        name_lower = name.lower()
        if name_lower in self.CP_REGISTERS:
            return self.CP_REGISTERS[name_lower]
        return None
    
    def get_fpu_reg(self, name):
        """Get FPU register address by name"""
        name_lower = name.lower()
        if name_lower in self.FPU_REGISTERS:
            return self.FPU_REGISTERS[name_lower]
        return None
    
    def get_vfp_reg(self, name):
        """Get VFP register address by name"""
        name_lower = name.lower()
        if name_lower in self.VFP_REGISTERS:
            return self.VFP_REGISTERS[name_lower]
        return None
    
    def is_core_reg(self, name):
        """Check if register is a core register"""
        return name.lower() in self.CORE_REGISTERS
    
    def is_psr_reg(self, name):
        """Check if register is a PSR register"""
        return name.lower() in self.PSR_REGISTERS
    
    def is_cp_hyp_reg(self, name):
        """Check if register is a CP HYP register"""
        name_lower = name.lower()
        return (name_lower in self.CP_HYP_REGISTERS or 
                name_lower in self.CP_HYP_REGISTERS_64)
    
    def is_debug_reg(self, name):
        """Check if register is a debug register"""
        name_lower = name.lower()
        return (name_lower in self.DEBUG_REGISTERS or 
                name_lower in self.DEBUG_CP15_REGISTERS)
    
    def is_cp_reg(self, name):
        """Check if register is a CP15 register"""
        return name.lower() in self.CP_REGISTERS
    
    def is_fpu_reg(self, name):
        """Check if register is an FPU register"""
        return name.lower() in self.FPU_REGISTERS
    
    def is_vfp_reg(self, name):
        """Check if register is a VFP register"""
        return name.lower() in self.VFP_REGISTERS
