# -*- coding: utf-8 -*-
"""
 Copyright 2025 NXP

 NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be
 used strictly in accordance with the applicable license terms. By expressly
 accepting such terms or by downloading, installing, activating and/or otherwise
 using the software, you are agreeing that you have read, and that you agree to
 comply with and are bound by, such license terms. If you do not agree to be
 bound by the applicable license terms, then you may not retain, install,
 activate or otherwise use the software.

"""

class SPT3Registers:
    """
    SPT3 processor register definitions

    """
    
    # Base addresses from TCL file
    DEBUG_REGISTERS_FIRST = 0x3000
    WORK_REGISTERS_FIRST = 0x1000
    SPR_REGISTERS_FIRST = 0x2000
    
    # Debug Registers
    # Formula: debug_registers_first + (reg & 0x3ff)
    DEBUG_REGISTERS = {
        "gbl_ctrl": DEBUG_REGISTERS_FIRST + (0 & 0x3ff),
        "cs_pg_st_addr": DEBUG_REGISTERS_FIRST + (1 & 0x3ff),
        "cs_mode_ctrl": DEBUG_REGISTERS_FIRST + (2 & 0x3ff),
        "cs_wd_status": DEBUG_REGISTERS_FIRST + (3 & 0x3ff),
        "cs_bkpt0_addr": DEBUG_REGISTERS_FIRST + (4 & 0x3ff),
        "cs_bkpt1_addr": DEBUG_REGISTERS_FIRST + (5 & 0x3ff),
        "cs_bkpt2_addr": DEBUG_REGISTERS_FIRST + (6 & 0x3ff),
        "cs_bkpt3_addr": DEBUG_REGISTERS_FIRST + (7 & 0x3ff),
        "cs_jam_inst0": DEBUG_REGISTERS_FIRST + (8 & 0x3ff),
        "cs_jam_inst1": DEBUG_REGISTERS_FIRST + (9 & 0x3ff),
        "cs_jam_inst2": DEBUG_REGISTERS_FIRST + (10 & 0x3ff),
        "cs_jam_inst3": DEBUG_REGISTERS_FIRST + (11 & 0x3ff),
        "cs_curr_inst_addr": DEBUG_REGISTERS_FIRST + (12 & 0x3ff),
        "cs_curr_inst0": DEBUG_REGISTERS_FIRST + (13 & 0x3ff),
        "cs_curr_inst1": DEBUG_REGISTERS_FIRST + (14 & 0x3ff),
        "cs_curr_inst2": DEBUG_REGISTERS_FIRST + (15 & 0x3ff),
        "cs_curr_inst3": DEBUG_REGISTERS_FIRST + (16 & 0x3ff),
        "cs_loopcntr01": DEBUG_REGISTERS_FIRST + (17 & 0x3ff),
        "cs_loopcntr23": DEBUG_REGISTERS_FIRST + (18 & 0x3ff),
        "cs_err_inst_addr": DEBUG_REGISTERS_FIRST + (19 & 0x3ff),
        "cs_err_inst0": DEBUG_REGISTERS_FIRST + (20 & 0x3ff),
        "cs_err_inst1": DEBUG_REGISTERS_FIRST + (21 & 0x3ff),
        "cs_err_inst2": DEBUG_REGISTERS_FIRST + (22 & 0x3ff),
        "cs_err_inst3": DEBUG_REGISTERS_FIRST + (23 & 0x3ff),
        "cs_status0": DEBUG_REGISTERS_FIRST + (24 & 0x3ff),
        "cs_status1": DEBUG_REGISTERS_FIRST + (25 & 0x3ff),
        "cs_status2": DEBUG_REGISTERS_FIRST + (26 & 0x3ff),
        "cs_status3": DEBUG_REGISTERS_FIRST + (27 & 0x3ff),
        "cs_evtreg1": DEBUG_REGISTERS_FIRST + (28 & 0x3ff),
        "cs_sw_evtreg": DEBUG_REGISTERS_FIRST + (30 & 0x3ff),
        "cs_chrp_cntr_rst": DEBUG_REGISTERS_FIRST + (32 & 0x3ff),
        "cs_chrp_cntr_ld": DEBUG_REGISTERS_FIRST + (33 & 0x3ff),
        "cs_inten0": DEBUG_REGISTERS_FIRST + (34 & 0x3ff),
        "cs_inten1": DEBUG_REGISTERS_FIRST + (35 & 0x3ff),
        "cs_evt1_inten": DEBUG_REGISTERS_FIRST + (36 & 0x3ff),
        "dsp_rst_reg": DEBUG_REGISTERS_FIRST + (37 & 0x3ff),
        "dsp_config_reg": DEBUG_REGISTERS_FIRST + (38 & 0x3ff),
        "dsp_err_info_reg": DEBUG_REGISTERS_FIRST + (39 & 0x3ff),
        "dsp_err_info_int_en": DEBUG_REGISTERS_FIRST + (40 & 0x3ff),
        "dsp_pfault_info_reg": DEBUG_REGISTERS_FIRST + (41 & 0x3ff),
        "dsp_debug1_reg": DEBUG_REGISTERS_FIRST + (42 & 0x3ff),
        "dsp_debug2_reg": DEBUG_REGISTERS_FIRST + (43 & 0x3ff),
        "dsp_debug3_reg": DEBUG_REGISTERS_FIRST + (44 & 0x3ff),
        "dsp_debug4_reg": DEBUG_REGISTERS_FIRST + (45 & 0x3ff),
        "dsp_debug5_reg": DEBUG_REGISTERS_FIRST + (46 & 0x3ff),
        "dsp_debug6_reg": DEBUG_REGISTERS_FIRST + (47 & 0x3ff),
        "pdma_lfsr_load_val_high": DEBUG_REGISTERS_FIRST + (48 & 0x3ff),
        "pdma_lfsr_load_val_low": DEBUG_REGISTERS_FIRST + (49 & 0x3ff),
        "pdma_control": DEBUG_REGISTERS_FIRST + (50 & 0x3ff),
        "pdma_transfer_count_status": DEBUG_REGISTERS_FIRST + (51 & 0x3ff),
        "pdma_fmtb_exp_addr_status": DEBUG_REGISTERS_FIRST + (52 & 0x3ff),
        "hist_ovf_status0": DEBUG_REGISTERS_FIRST + (56 & 0x3ff),
        "hist_ovf_status1": DEBUG_REGISTERS_FIRST + (57 & 0x3ff),
        "hist_ovf_ie": DEBUG_REGISTERS_FIRST + (58 & 0x3ff),
        "mem_err_inject_ctrl": DEBUG_REGISTERS_FIRST + (64 & 0x3ff),
        "mem_err_ststus": DEBUG_REGISTERS_FIRST + (65 & 0x3ff),
        "mem_err_int_en": DEBUG_REGISTERS_FIRST + (66 & 0x3ff),
        "or_wr_lock_err_thrd_status": DEBUG_REGISTERS_FIRST + (67 & 0x3ff),
        "or_rd_lock_err_thrd_status": DEBUG_REGISTERS_FIRST + (68 & 0x3ff),
        "tr_wr_lock_err_thrd_status": DEBUG_REGISTERS_FIRST + (69 & 0x3ff),
        "tr_rd_lock_err_thrd_status": DEBUG_REGISTERS_FIRST + (70 & 0x3ff),
        "or_west_wr_lock_err_addr": DEBUG_REGISTERS_FIRST + (71 & 0x3ff),
        "or_east_wr_lock_err_addr": DEBUG_REGISTERS_FIRST + (72 & 0x3ff),
        "or_west_rd_lock_err_addr": DEBUG_REGISTERS_FIRST + (73 & 0x3ff),
        "or_east_rd_lock_err_addr": DEBUG_REGISTERS_FIRST + (74 & 0x3ff),
        "tr_wr_lock_err_addr": DEBUG_REGISTERS_FIRST + (75 & 0x3ff),
        "tr_rd_lock_err_addr": DEBUG_REGISTERS_FIRST + (76 & 0x3ff),
        "or_west_par_err_addr": DEBUG_REGISTERS_FIRST + (77 & 0x3ff),
        "or_east_par_err_addr": DEBUG_REGISTERS_FIRST + (78 & 0x3ff),
        "tr_par_err_addr": DEBUG_REGISTERS_FIRST + (79 & 0x3ff),
        "spt_axi_qos_rd": DEBUG_REGISTERS_FIRST + (84 & 0x3ff),
        "spt_axi_qos_wr": DEBUG_REGISTERS_FIRST + (85 & 0x3ff),
        "dma_err_status": DEBUG_REGISTERS_FIRST + (86 & 0x3ff),
        "gbl_status": DEBUG_REGISTERS_FIRST + (87 & 0x3ff),
        "bl_status_ie": DEBUG_REGISTERS_FIRST + (88 & 0x3ff),
        "hw_acc_err_status": DEBUG_REGISTERS_FIRST + (89 & 0x3ff),
        "hw_acc_err_ie": DEBUG_REGISTERS_FIRST + (90 & 0x3ff),
        "hw2_acc_err_status": DEBUG_REGISTERS_FIRST + (91 & 0x3ff),
        "hw2_acc_err_ie": DEBUG_REGISTERS_FIRST + (92 & 0x3ff),
        "wr_access_err_reg": DEBUG_REGISTERS_FIRST + (93 & 0x3ff),
        "wr_access_err_int_en": DEBUG_REGISTERS_FIRST + (94 & 0x3ff),
        "wr_0_15_ctrl_reg": DEBUG_REGISTERS_FIRST + (96 & 0x3ff),
        "wr_16_31_ctrl_reg": DEBUG_REGISTERS_FIRST + (97 & 0x3ff),
        "wr_32_47_ctrl_reg": DEBUG_REGISTERS_FIRST + (98 & 0x3ff),
        "wr_r0_re": DEBUG_REGISTERS_FIRST + (102 & 0x3ff),
        "wr_r0_im": DEBUG_REGISTERS_FIRST + (103 & 0x3ff),
        "wr_r1_re": DEBUG_REGISTERS_FIRST + (104 & 0x3ff),
        "wr_r1_im": DEBUG_REGISTERS_FIRST + (105 & 0x3ff),
        "wr_r2_re": DEBUG_REGISTERS_FIRST + (106 & 0x3ff),
        "wr_r2_im": DEBUG_REGISTERS_FIRST + (107 & 0x3ff),
        "wr_r3_re": DEBUG_REGISTERS_FIRST + (108 & 0x3ff),
        "wr_r3_im": DEBUG_REGISTERS_FIRST + (109 & 0x3ff),
        "wr_r4_re": DEBUG_REGISTERS_FIRST + (110 & 0x3ff),
        "wr_r4_im": DEBUG_REGISTERS_FIRST + (111 & 0x3ff),
        "wr_r5_re": DEBUG_REGISTERS_FIRST + (112 & 0x3ff),
        "wr_r5_im": DEBUG_REGISTERS_FIRST + (113 & 0x3ff),
        "wr_r6_re": DEBUG_REGISTERS_FIRST + (114 & 0x3ff),
        "wr_r6_im": DEBUG_REGISTERS_FIRST + (115 & 0x3ff),
        "wr_r7_re": DEBUG_REGISTERS_FIRST + (116 & 0x3ff),
        "wr_r7_im": DEBUG_REGISTERS_FIRST + (117 & 0x3ff),
        "wr_r8_re": DEBUG_REGISTERS_FIRST + (118 & 0x3ff),
        "wr_r8_im": DEBUG_REGISTERS_FIRST + (119 & 0x3ff),
        "wr_r9_re": DEBUG_REGISTERS_FIRST + (120 & 0x3ff),
        "wr_r9_im": DEBUG_REGISTERS_FIRST + (121 & 0x3ff),
        "wr_r10_re": DEBUG_REGISTERS_FIRST + (122 & 0x3ff),
        "wr_r10_im": DEBUG_REGISTERS_FIRST + (123 & 0x3ff),
        "wr_r11_re": DEBUG_REGISTERS_FIRST + (124 & 0x3ff),
        "wr_r11_im": DEBUG_REGISTERS_FIRST + (125 & 0x3ff),
        "wr_r12_re": DEBUG_REGISTERS_FIRST + (126 & 0x3ff),
        "wr_r12_im": DEBUG_REGISTERS_FIRST + (127 & 0x3ff),
        "wr_r13_re": DEBUG_REGISTERS_FIRST + (128 & 0x3ff),
        "wr_r13_im": DEBUG_REGISTERS_FIRST + (129 & 0x3ff),
        "wr_r14_re": DEBUG_REGISTERS_FIRST + (130 & 0x3ff),
        "wr_r14_im": DEBUG_REGISTERS_FIRST + (131 & 0x3ff),
        "wr_r15_re": DEBUG_REGISTERS_FIRST + (132 & 0x3ff),
        "wr_r15_im": DEBUG_REGISTERS_FIRST + (133 & 0x3ff),
        "wr_r16_re": DEBUG_REGISTERS_FIRST + (134 & 0x3ff),
        "wr_r16_im": DEBUG_REGISTERS_FIRST + (135 & 0x3ff),
        "wr_r17_re": DEBUG_REGISTERS_FIRST + (136 & 0x3ff),
        "wr_r17_im": DEBUG_REGISTERS_FIRST + (137 & 0x3ff),
        "wr_r18_re": DEBUG_REGISTERS_FIRST + (138 & 0x3ff),
        "wr_r18_im": DEBUG_REGISTERS_FIRST + (139 & 0x3ff),
        "wr_r19_re": DEBUG_REGISTERS_FIRST + (140 & 0x3ff),
        "wr_r19_im": DEBUG_REGISTERS_FIRST + (141 & 0x3ff),
        "wr_r20_re": DEBUG_REGISTERS_FIRST + (142 & 0x3ff),
        "wr_r20_im": DEBUG_REGISTERS_FIRST + (143 & 0x3ff),
        "wr_r21_re": DEBUG_REGISTERS_FIRST + (144 & 0x3ff),
        "wr_r21_im": DEBUG_REGISTERS_FIRST + (145 & 0x3ff),
        "wr_r22_re": DEBUG_REGISTERS_FIRST + (146 & 0x3ff),
        "wr_r22_im": DEBUG_REGISTERS_FIRST + (147 & 0x3ff),
        "wr_r23_re": DEBUG_REGISTERS_FIRST + (148 & 0x3ff),
        "wr_r23_im": DEBUG_REGISTERS_FIRST + (149 & 0x3ff),
        "wr_r24_re": DEBUG_REGISTERS_FIRST + (150 & 0x3ff),
        "wr_r24_im": DEBUG_REGISTERS_FIRST + (151 & 0x3ff),
        "wr_r25_re": DEBUG_REGISTERS_FIRST + (152 & 0x3ff),
        "wr_r25_im": DEBUG_REGISTERS_FIRST + (153 & 0x3ff),
        "wr_r26_re": DEBUG_REGISTERS_FIRST + (154 & 0x3ff),
        "wr_r26_im": DEBUG_REGISTERS_FIRST + (155 & 0x3ff),
        "wr_r27_re": DEBUG_REGISTERS_FIRST + (156 & 0x3ff),
        "wr_r27_im": DEBUG_REGISTERS_FIRST + (157 & 0x3ff),
        "wr_r28_re": DEBUG_REGISTERS_FIRST + (158 & 0x3ff),
        "wr_r28_im": DEBUG_REGISTERS_FIRST + (159 & 0x3ff),
        "wr_r29_re": DEBUG_REGISTERS_FIRST + (160 & 0x3ff),
        "wr_r29_im": DEBUG_REGISTERS_FIRST + (161 & 0x3ff),
        "wr_r30_re": DEBUG_REGISTERS_FIRST + (162 & 0x3ff),
        "wr_r30_im": DEBUG_REGISTERS_FIRST + (163 & 0x3ff),
        "wr_r31_re": DEBUG_REGISTERS_FIRST + (164 & 0x3ff),
        "wr_r31_im": DEBUG_REGISTERS_FIRST + (165 & 0x3ff),
        "wr_r32_re": DEBUG_REGISTERS_FIRST + (166 & 0x3ff),
        "wr_r32_im": DEBUG_REGISTERS_FIRST + (167 & 0x3ff),
        "wr_r33_re": DEBUG_REGISTERS_FIRST + (168 & 0x3ff),
        "wr_r33_im": DEBUG_REGISTERS_FIRST + (169 & 0x3ff),
        "wr_r34_re": DEBUG_REGISTERS_FIRST + (170 & 0x3ff),
        "wr_r34_im": DEBUG_REGISTERS_FIRST + (171 & 0x3ff),
        "wr_r35_re": DEBUG_REGISTERS_FIRST + (172 & 0x3ff),
        "wr_r35_im": DEBUG_REGISTERS_FIRST + (173 & 0x3ff),
        "wr_r36_re": DEBUG_REGISTERS_FIRST + (174 & 0x3ff),
        "wr_r36_im": DEBUG_REGISTERS_FIRST + (175 & 0x3ff),
        "wr_r37_re": DEBUG_REGISTERS_FIRST + (176 & 0x3ff),
        "wr_r37_im": DEBUG_REGISTERS_FIRST + (177 & 0x3ff),
        "wr_r38_re": DEBUG_REGISTERS_FIRST + (178 & 0x3ff),
        "wr_r38_im": DEBUG_REGISTERS_FIRST + (179 & 0x3ff),
        "wr_r39_re": DEBUG_REGISTERS_FIRST + (180 & 0x3ff),
        "wr_r39_im": DEBUG_REGISTERS_FIRST + (181 & 0x3ff),
        "wr_r40_re": DEBUG_REGISTERS_FIRST + (182 & 0x3ff),
        "wr_r40_im": DEBUG_REGISTERS_FIRST + (183 & 0x3ff),
        "wr_r41_re": DEBUG_REGISTERS_FIRST + (184 & 0x3ff),
        "wr_r41_im": DEBUG_REGISTERS_FIRST + (185 & 0x3ff),
        "wr_r42_re": DEBUG_REGISTERS_FIRST + (186 & 0x3ff),
        "wr_r42_im": DEBUG_REGISTERS_FIRST + (187 & 0x3ff),
        "wr_r43_re": DEBUG_REGISTERS_FIRST + (188 & 0x3ff),
        "wr_r43_im": DEBUG_REGISTERS_FIRST + (189 & 0x3ff),
        "wr_r44_re": DEBUG_REGISTERS_FIRST + (190 & 0x3ff),
        "wr_r44_im": DEBUG_REGISTERS_FIRST + (191 & 0x3ff),
        "wr_r45_re": DEBUG_REGISTERS_FIRST + (192 & 0x3ff),
        "wr_r45_im": DEBUG_REGISTERS_FIRST + (193 & 0x3ff),
        "wr_r46_re": DEBUG_REGISTERS_FIRST + (194 & 0x3ff),
        "wr_r46_im": DEBUG_REGISTERS_FIRST + (195 & 0x3ff),
        "wr_r47_re": DEBUG_REGISTERS_FIRST + (196 & 0x3ff),
        "wr_r47_im": DEBUG_REGISTERS_FIRST + (197 & 0x3ff),
    }
    
    # SCS Debug Registers
    SCS_DEBUG_REGISTERS = {
        "scs0_jan_inst0": DEBUG_REGISTERS_FIRST + (256 & 0x3ff),
        "scs0_jan_inst1": DEBUG_REGISTERS_FIRST + (257 & 0x3ff),
        "scs0_jan_inst2": DEBUG_REGISTERS_FIRST + (258 & 0x3ff),
        "scs0_jan_inst3": DEBUG_REGISTERS_FIRST + (259 & 0x3ff),
        "scs0_curr_inst_addr": DEBUG_REGISTERS_FIRST + (260 & 0x3ff),
        "scs0_curr_inst0": DEBUG_REGISTERS_FIRST + (261 & 0x3ff),
        "scs0_curr_inst1": DEBUG_REGISTERS_FIRST + (262 & 0x3ff),
        "scs0_curr_inst2": DEBUG_REGISTERS_FIRST + (263 & 0x3ff),
        "scs0_curr_inst3": DEBUG_REGISTERS_FIRST + (264 & 0x3ff),
        "scs0_loopcntr01": DEBUG_REGISTERS_FIRST + (265 & 0x3ff),
        "scs0_loopcntr23": DEBUG_REGISTERS_FIRST + (266 & 0x3ff),
        "scs0_err_inst_addr": DEBUG_REGISTERS_FIRST + (267 & 0x3ff),
        "scs0_err_inst0": DEBUG_REGISTERS_FIRST + (268 & 0x3ff),
        "scs0_err_inst1": DEBUG_REGISTERS_FIRST + (269 & 0x3ff),
        "scs0_err_inst2": DEBUG_REGISTERS_FIRST + (270 & 0x3ff),
        "scs0_err_inst3": DEBUG_REGISTERS_FIRST + (271 & 0x3ff),
        "scs0_status0": DEBUG_REGISTERS_FIRST + (272 & 0x3ff),
        "scs0_status1": DEBUG_REGISTERS_FIRST + (273 & 0x3ff),
        "scs0_status2": DEBUG_REGISTERS_FIRST + (274 & 0x3ff),
        "scs0_status3": DEBUG_REGISTERS_FIRST + (275 & 0x3ff),
        "scs0_inten0": DEBUG_REGISTERS_FIRST + (276 & 0x3ff),
        "scs0_inten1": DEBUG_REGISTERS_FIRST + (277 & 0x3ff),
        "scs0_pdma_transfer_count_status": DEBUG_REGISTERS_FIRST + (278 & 0x3ff),
        "scs0_pdma_fmtb_exp_addr_status": DEBUG_REGISTERS_FIRST + (279 & 0x3ff),
        "scs1_jam_inst0": DEBUG_REGISTERS_FIRST + (296 & 0x3ff),
        "scs1_jam_inst1": DEBUG_REGISTERS_FIRST + (297 & 0x3ff),
        "scs1_jam_inst2": DEBUG_REGISTERS_FIRST + (298 & 0x3ff),
        "scs1_jam_inst3": DEBUG_REGISTERS_FIRST + (299 & 0x3ff),
        "scs1_curr_inst_addr": DEBUG_REGISTERS_FIRST + (300 & 0x3ff),
        "scs1_curr_inst0": DEBUG_REGISTERS_FIRST + (301 & 0x3ff),
        "scs1_curr_inst1": DEBUG_REGISTERS_FIRST + (302 & 0x3ff),
        "scs1_curr_inst2": DEBUG_REGISTERS_FIRST + (303 & 0x3ff),
        "scs1_curr_inst3": DEBUG_REGISTERS_FIRST + (304 & 0x3ff),
        "scs1_loopcntr01": DEBUG_REGISTERS_FIRST + (305 & 0x3ff),
        "scs1_loopcntr23": DEBUG_REGISTERS_FIRST + (306 & 0x3ff),
        "scs1_err_inst_addr": DEBUG_REGISTERS_FIRST + (307 & 0x3ff),
        "scs1_err_inst0": DEBUG_REGISTERS_FIRST + (308 & 0x3ff),
        "scs1_err_inst1": DEBUG_REGISTERS_FIRST + (309 & 0x3ff),
        "scs1_err_inst2": DEBUG_REGISTERS_FIRST + (310 & 0x3ff),
        "scs1_err_inst3": DEBUG_REGISTERS_FIRST + (311 & 0x3ff),
        "scs1_status0": DEBUG_REGISTERS_FIRST + (312 & 0x3ff),
        "scs1_status1": DEBUG_REGISTERS_FIRST + (313 & 0x3ff),
        "scs1_status2": DEBUG_REGISTERS_FIRST + (314 & 0x3ff),
        "scs1_status3": DEBUG_REGISTERS_FIRST + (315 & 0x3ff),
        "scs1_inten0": DEBUG_REGISTERS_FIRST + (316 & 0x3ff),
        "scs1_inten1": DEBUG_REGISTERS_FIRST + (317 & 0x3ff),
        "scs1_pdma_transfer_count_status": DEBUG_REGISTERS_FIRST + (318 & 0x3ff),
        "scs1_pdma_fmtb_exp_addr_status": DEBUG_REGISTERS_FIRST + (319 & 0x3ff),
        "scs2_jam_inst0": DEBUG_REGISTERS_FIRST + (336 & 0x3ff),
        "scs2_jam_inst1": DEBUG_REGISTERS_FIRST + (337 & 0x3ff),
        "scs2_jam_inst2": DEBUG_REGISTERS_FIRST + (338 & 0x3ff),
        "scs2_jam_inst3": DEBUG_REGISTERS_FIRST + (339 & 0x3ff),
        "scs2_curr_inst_addr": DEBUG_REGISTERS_FIRST + (340 & 0x3ff),
        "scs2_curr_inst0": DEBUG_REGISTERS_FIRST + (341 & 0x3ff),
        "scs2_curr_inst1": DEBUG_REGISTERS_FIRST + (342 & 0x3ff),
        "scs2_curr_inst2": DEBUG_REGISTERS_FIRST + (343 & 0x3ff),
        "scs2_curr_inst3": DEBUG_REGISTERS_FIRST + (344 & 0x3ff),
        "scs2_loopcntr01": DEBUG_REGISTERS_FIRST + (345 & 0x3ff),
        "scs2_loopcntr23": DEBUG_REGISTERS_FIRST + (346 & 0x3ff),
        "scs2_err_inst_addr": DEBUG_REGISTERS_FIRST + (347 & 0x3ff),
        "scs2_err_inst0": DEBUG_REGISTERS_FIRST + (348 & 0x3ff),
        "scs2_err_inst1": DEBUG_REGISTERS_FIRST + (349 & 0x3ff),
        "scs2_err_inst2": DEBUG_REGISTERS_FIRST + (350 & 0x3ff),
        "scs2_err_inst3": DEBUG_REGISTERS_FIRST + (351 & 0x3ff),
        "scs2_status0": DEBUG_REGISTERS_FIRST + (352 & 0x3ff),
        "scs2_status1": DEBUG_REGISTERS_FIRST + (353 & 0x3ff),
        "scs2_status2": DEBUG_REGISTERS_FIRST + (354 & 0x3ff),
        "scs2_status3": DEBUG_REGISTERS_FIRST + (355 & 0x3ff),
        "scs2_inten0": DEBUG_REGISTERS_FIRST + (356 & 0x3ff),
        "scs2_inten1": DEBUG_REGISTERS_FIRST + (357 & 0x3ff),
        "scs2_pdma_transfer_count_status": DEBUG_REGISTERS_FIRST + (358 & 0x3ff),
        "scs2_pdma_fmtb_exp_addr_status": DEBUG_REGISTERS_FIRST + (359 & 0x3ff),
        "scs3_jam_inst0": DEBUG_REGISTERS_FIRST + (376 & 0x3ff),
        "scs3_jam_inst1": DEBUG_REGISTERS_FIRST + (377 & 0x3ff),
        "scs3_jam_inst2": DEBUG_REGISTERS_FIRST + (378 & 0x3ff),
        "scs3_jam_inst3": DEBUG_REGISTERS_FIRST + (379 & 0x3ff),
        "scs3_curr_inst_addr": DEBUG_REGISTERS_FIRST + (380 & 0x3ff),
        "scs3_curr_inst0": DEBUG_REGISTERS_FIRST + (381 & 0x3ff),
        "scs3_curr_inst1": DEBUG_REGISTERS_FIRST + (382 & 0x3ff),
        "scs3_curr_inst2": DEBUG_REGISTERS_FIRST + (383 & 0x3ff),
        "scs3_curr_inst3": DEBUG_REGISTERS_FIRST + (384 & 0x3ff),
        "scs3_loopcntr01": DEBUG_REGISTERS_FIRST + (385 & 0x3ff),
        "scs3_loopcntr23": DEBUG_REGISTERS_FIRST + (386 & 0x3ff),
        "scs3_err_inst_addr": DEBUG_REGISTERS_FIRST + (387 & 0x3ff),
        "scs3_err_inst0": DEBUG_REGISTERS_FIRST + (388 & 0x3ff),
        "scs3_err_inst1": DEBUG_REGISTERS_FIRST + (389 & 0x3ff),
        "scs3_err_inst2": DEBUG_REGISTERS_FIRST + (390 & 0x3ff),
        "scs3_err_inst3": DEBUG_REGISTERS_FIRST + (391 & 0x3ff),
        "scs3_status0": DEBUG_REGISTERS_FIRST + (392 & 0x3ff),
        "scs3_status1": DEBUG_REGISTERS_FIRST + (393 & 0x3ff),
        "scs3_status2": DEBUG_REGISTERS_FIRST + (394 & 0x3ff),
        "scs3_status3": DEBUG_REGISTERS_FIRST + (395 & 0x3ff),
        "scs3_inten0": DEBUG_REGISTERS_FIRST + (396 & 0x3ff),
        "scs3_inten1": DEBUG_REGISTERS_FIRST + (397 & 0x3ff),
        "scs3_pdma_transfer_count_status": DEBUG_REGISTERS_FIRST + (398 & 0x3ff),
        "scs3_pdma_fmtb_exp_addr_status": DEBUG_REGISTERS_FIRST + (399 & 0x3ff),
    }
    
    # SPR Control and Event Registers
    SPR_CONTROL_REGISTERS = {
        "spr_0_15_ctrl_reg": DEBUG_REGISTERS_FIRST + (512 & 0x3ff),
        "spr0_re": DEBUG_REGISTERS_FIRST + (516 & 0x3ff),
        "spr0_im": DEBUG_REGISTERS_FIRST + (517 & 0x3ff),
        "spr1_re": DEBUG_REGISTERS_FIRST + (518 & 0x3ff),
        "spr1_im": DEBUG_REGISTERS_FIRST + (519 & 0x3ff),
        "spr2_re": DEBUG_REGISTERS_FIRST + (520 & 0x3ff),
        "spr2_im": DEBUG_REGISTERS_FIRST + (521 & 0x3ff),
        "spr3_re": DEBUG_REGISTERS_FIRST + (522 & 0x3ff),
        "spr3_im": DEBUG_REGISTERS_FIRST + (523 & 0x3ff),
        "spr4_re": DEBUG_REGISTERS_FIRST + (524 & 0x3ff),
        "spr4_im": DEBUG_REGISTERS_FIRST + (525 & 0x3ff),
        "spr5_re": DEBUG_REGISTERS_FIRST + (526 & 0x3ff),
        "spr5_im": DEBUG_REGISTERS_FIRST + (527 & 0x3ff),
        "spr6_re": DEBUG_REGISTERS_FIRST + (528 & 0x3ff),
        "spr6_im": DEBUG_REGISTERS_FIRST + (529 & 0x3ff),
        "spr7_re": DEBUG_REGISTERS_FIRST + (530 & 0x3ff),
        "spr7_im": DEBUG_REGISTERS_FIRST + (531 & 0x3ff),
        "spr8_re": DEBUG_REGISTERS_FIRST + (532 & 0x3ff),
        "spr8_im": DEBUG_REGISTERS_FIRST + (533 & 0x3ff),
        "spr9_re": DEBUG_REGISTERS_FIRST + (534 & 0x3ff),
        "spr9_im": DEBUG_REGISTERS_FIRST + (535 & 0x3ff),
        "hw_spr0_re": DEBUG_REGISTERS_FIRST + (548 & 0x3ff),
        "hw_spr0_im": DEBUG_REGISTERS_FIRST + (549 & 0x3ff),
        "hw_spr1_re": DEBUG_REGISTERS_FIRST + (550 & 0x3ff),
        "hw_spr1_im": DEBUG_REGISTERS_FIRST + (551 & 0x3ff),
        "hw_spr2_re": DEBUG_REGISTERS_FIRST + (552 & 0x3ff),
        "hw_spr2_im": DEBUG_REGISTERS_FIRST + (553 & 0x3ff),
        "hw_spr3_re": DEBUG_REGISTERS_FIRST + (554 & 0x3ff),
        "hw_spr3_im": DEBUG_REGISTERS_FIRST + (555 & 0x3ff),
        "hw_spr4_re": DEBUG_REGISTERS_FIRST + (556 & 0x3ff),
        "hw_spr4_im": DEBUG_REGISTERS_FIRST + (557 & 0x3ff),
        "hw_spr5_re": DEBUG_REGISTERS_FIRST + (558 & 0x3ff),
        "hw_spr5_im": DEBUG_REGISTERS_FIRST + (559 & 0x3ff),
        "evt_spr0_re": DEBUG_REGISTERS_FIRST + (560 & 0x3ff),
        "evt_spr0_im": DEBUG_REGISTERS_FIRST + (561 & 0x3ff),
        "evt_spr1_re": DEBUG_REGISTERS_FIRST + (562 & 0x3ff),
        "evt_spr1_im": DEBUG_REGISTERS_FIRST + (563 & 0x3ff),
        "evt_spr2_re": DEBUG_REGISTERS_FIRST + (564 & 0x3ff),
        "evt_spr2_im": DEBUG_REGISTERS_FIRST + (565 & 0x3ff),
        "evt_spr3_re": DEBUG_REGISTERS_FIRST + (566 & 0x3ff),
        "evt_spr3_im": DEBUG_REGISTERS_FIRST + (567 & 0x3ff),
        "evt_spr4_re": DEBUG_REGISTERS_FIRST + (568 & 0x3ff),
        "evt_spr4_im": DEBUG_REGISTERS_FIRST + (569 & 0x3ff),
        "evt_spr5_re": DEBUG_REGISTERS_FIRST + (570 & 0x3ff),
        "evt_spr5_im": DEBUG_REGISTERS_FIRST + (571 & 0x3ff),
        "evt_spr6_re": DEBUG_REGISTERS_FIRST + (572 & 0x3ff),
        "evt_spr6_im": DEBUG_REGISTERS_FIRST + (573 & 0x3ff),
        "evt_spr7_re": DEBUG_REGISTERS_FIRST + (574 & 0x3ff),
        "evt_spr7_im": DEBUG_REGISTERS_FIRST + (575 & 0x3ff),
        "evt_spr8_re": DEBUG_REGISTERS_FIRST + (576 & 0x3ff),
        "evt_spr8_im": DEBUG_REGISTERS_FIRST + (577 & 0x3ff),
        "evt_spr9_re": DEBUG_REGISTERS_FIRST + (578 & 0x3ff),
        "evt_spr9_im": DEBUG_REGISTERS_FIRST + (579 & 0x3ff),
        "chrp_spr0_re": DEBUG_REGISTERS_FIRST + (580 & 0x3ff),
        "chrp_spr0_im": DEBUG_REGISTERS_FIRST + (581 & 0x3ff),
        "chrp_spr1_re": DEBUG_REGISTERS_FIRST + (582 & 0x3ff),
        "chrp_spr1_im": DEBUG_REGISTERS_FIRST + (583 & 0x3ff),
        "chrp_spr2_re": DEBUG_REGISTERS_FIRST + (584 & 0x3ff),
        "chrp_spr2_im": DEBUG_REGISTERS_FIRST + (585 & 0x3ff),
        "chrp_spr3_re": DEBUG_REGISTERS_FIRST + (586 & 0x3ff),
        "chrp_spr3_im": DEBUG_REGISTERS_FIRST + (587 & 0x3ff),
        "chrp_spr4_re": DEBUG_REGISTERS_FIRST + (588 & 0x3ff),
        "chrp_spr4_im": DEBUG_REGISTERS_FIRST + (589 & 0x3ff),
        "chrp_spr5_re": DEBUG_REGISTERS_FIRST + (590 & 0x3ff),
        "chrp_spr5_im": DEBUG_REGISTERS_FIRST + (591 & 0x3ff),
        "chrp_spr6_re": DEBUG_REGISTERS_FIRST + (592 & 0x3ff),
        "chrp_spr6_im": DEBUG_REGISTERS_FIRST + (593 & 0x3ff),
        "chrp_spr7_re": DEBUG_REGISTERS_FIRST + (594 & 0x3ff),
        "chrp_spr7_im": DEBUG_REGISTERS_FIRST + (595 & 0x3ff),
    }
    
    # Work Registers
    # Formula: work_registers_first + (reg & 0x3f)
    WORK_REGISTERS = {
        "wr0": WORK_REGISTERS_FIRST + (0 & 0x3f),
        "wr1": WORK_REGISTERS_FIRST + (1 & 0x3f),
        "wr2": WORK_REGISTERS_FIRST + (2 & 0x3f),
        "wr3": WORK_REGISTERS_FIRST + (3 & 0x3f),
        "wr4": WORK_REGISTERS_FIRST + (4 & 0x3f),
        "wr5": WORK_REGISTERS_FIRST + (5 & 0x3f),
        "wr6": WORK_REGISTERS_FIRST + (6 & 0x3f),
        "wr7": WORK_REGISTERS_FIRST + (7 & 0x3f),
        "wr8": WORK_REGISTERS_FIRST + (8 & 0x3f),
        "wr9": WORK_REGISTERS_FIRST + (9 & 0x3f),
        "wr10": WORK_REGISTERS_FIRST + (10 & 0x3f),
        "wr11": WORK_REGISTERS_FIRST + (11 & 0x3f),
        "wr12": WORK_REGISTERS_FIRST + (12 & 0x3f),
        "wr13": WORK_REGISTERS_FIRST + (13 & 0x3f),
        "wr14": WORK_REGISTERS_FIRST + (14 & 0x3f),
        "wr15": WORK_REGISTERS_FIRST + (15 & 0x3f),
        "wr16": WORK_REGISTERS_FIRST + (16 & 0x3f),
        "wr17": WORK_REGISTERS_FIRST + (17 & 0x3f),
        "wr18": WORK_REGISTERS_FIRST + (18 & 0x3f),
        "wr19": WORK_REGISTERS_FIRST + (19 & 0x3f),
        "wr20": WORK_REGISTERS_FIRST + (20 & 0x3f),
        "wr21": WORK_REGISTERS_FIRST + (21 & 0x3f),
        "wr22": WORK_REGISTERS_FIRST + (22 & 0x3f),
        "wr23": WORK_REGISTERS_FIRST + (23 & 0x3f),
        "wr24": WORK_REGISTERS_FIRST + (24 & 0x3f),
        "wr25": WORK_REGISTERS_FIRST + (25 & 0x3f),
        "wr26": WORK_REGISTERS_FIRST + (26 & 0x3f),
        "wr27": WORK_REGISTERS_FIRST + (27 & 0x3f),
        "wr28": WORK_REGISTERS_FIRST + (28 & 0x3f),
        "wr29": WORK_REGISTERS_FIRST + (29 & 0x3f),
        "wr30": WORK_REGISTERS_FIRST + (30 & 0x3f),
        "wr31": WORK_REGISTERS_FIRST + (31 & 0x3f),
        "wr32": WORK_REGISTERS_FIRST + (32 & 0x3f),
        "wr33": WORK_REGISTERS_FIRST + (33 & 0x3f),
        "wr34": WORK_REGISTERS_FIRST + (34 & 0x3f),
        "wr35": WORK_REGISTERS_FIRST + (35 & 0x3f),
        "wr36": WORK_REGISTERS_FIRST + (36 & 0x3f),
        "wr37": WORK_REGISTERS_FIRST + (37 & 0x3f),
        "wr38": WORK_REGISTERS_FIRST + (38 & 0x3f),
        "wr39": WORK_REGISTERS_FIRST + (39 & 0x3f),
        "wr40": WORK_REGISTERS_FIRST + (40 & 0x3f),
        "wr41": WORK_REGISTERS_FIRST + (41 & 0x3f),
        "wr42": WORK_REGISTERS_FIRST + (42 & 0x3f),
        "wr43": WORK_REGISTERS_FIRST + (43 & 0x3f),
        "wr44": WORK_REGISTERS_FIRST + (44 & 0x3f),
        "wr45": WORK_REGISTERS_FIRST + (45 & 0x3f),
        "wr46": WORK_REGISTERS_FIRST + (46 & 0x3f),
        "wr47": WORK_REGISTERS_FIRST + (47 & 0x3f),
    }
    
    # SPR Registers
    # Formula: spr_registers_first + (reg & 0x3f)
    SPR_REGISTERS = {
        "spr0": SPR_REGISTERS_FIRST + (0 & 0x3f),
        "spr1": SPR_REGISTERS_FIRST + (1 & 0x3f),
        "spr2": SPR_REGISTERS_FIRST + (2 & 0x3f),
        "spr3": SPR_REGISTERS_FIRST + (3 & 0x3f),
        "spr4": SPR_REGISTERS_FIRST + (4 & 0x3f),
        "spr5": SPR_REGISTERS_FIRST + (5 & 0x3f),
        "spr6": SPR_REGISTERS_FIRST + (6 & 0x3f),
        "spr7": SPR_REGISTERS_FIRST + (7 & 0x3f),
        "spr8": SPR_REGISTERS_FIRST + (8 & 0x3f),
        "spr9": SPR_REGISTERS_FIRST + (9 & 0x3f),
        "hw_spr0": SPR_REGISTERS_FIRST + (16 & 0x3f),
        "hw_spr1": SPR_REGISTERS_FIRST + (17 & 0x3f),
        "hw_spr2": SPR_REGISTERS_FIRST + (18 & 0x3f),
        "hw_spr3": SPR_REGISTERS_FIRST + (19 & 0x3f),
        "hw_spr4": SPR_REGISTERS_FIRST + (20 & 0x3f),
        "hw_spr5": SPR_REGISTERS_FIRST + (21 & 0x3f),
        "evt_spr0": SPR_REGISTERS_FIRST + (22 & 0x3f),
        "evt_spr1": SPR_REGISTERS_FIRST + (23 & 0x3f),
        "evt_spr2": SPR_REGISTERS_FIRST + (24 & 0x3f),
        "evt_spr3": SPR_REGISTERS_FIRST + (25 & 0x3f),
        "evt_spr4": SPR_REGISTERS_FIRST + (26 & 0x3f),
        "evt_spr5": SPR_REGISTERS_FIRST + (27 & 0x3f),
        "evt_spr6": SPR_REGISTERS_FIRST + (28 & 0x3f),
        "evt_spr7": SPR_REGISTERS_FIRST + (29 & 0x3f),
        "evt_spr8": SPR_REGISTERS_FIRST + (30 & 0x3f),
        "evt_spr9": SPR_REGISTERS_FIRST + (31 & 0x3f),
        "chrp_spr0": SPR_REGISTERS_FIRST + (32 & 0x3f),
        "chrp_spr1": SPR_REGISTERS_FIRST + (33 & 0x3f),
        "chrp_spr2": SPR_REGISTERS_FIRST + (34 & 0x3f),
        "chrp_spr3": SPR_REGISTERS_FIRST + (35 & 0x3f),
        "chrp_spr4": SPR_REGISTERS_FIRST + (36 & 0x3f),
        "chrp_spr5": SPR_REGISTERS_FIRST + (37 & 0x3f),
        "chrp_spr6": SPR_REGISTERS_FIRST + (38 & 0x3f),
        "chrp_spr7": SPR_REGISTERS_FIRST + (39 & 0x3f),
    }
    
    # Register Aliases
    ALIASES = {}
    
    def __init__(self):
        """Initialize the SPT3 register manager"""
        self.all_registers = {}
        self.all_registers.update(self.DEBUG_REGISTERS)
        self.all_registers.update(self.SCS_DEBUG_REGISTERS)
        self.all_registers.update(self.SPR_CONTROL_REGISTERS)
        self.all_registers.update(self.WORK_REGISTERS)
        self.all_registers.update(self.SPR_REGISTERS)
    
    def get_address_by_name(self, name):
        """Get register address by name"""
        name_lower = name.lower()
        
        # Check aliases first
        if name_lower in self.ALIASES:
            name_lower = self.ALIASES[name_lower]
        
        if name_lower in self.all_registers:
            return self.all_registers[name_lower]
        return None
    
    def get_debug_reg(self, name):
        """Get debug register address by name"""
        name_lower = name.lower()
        if name_lower in self.DEBUG_REGISTERS:
            return self.DEBUG_REGISTERS[name_lower]
        return None
    
    def get_scs_debug_reg(self, name):
        """Get SCS debug register address by name"""
        name_lower = name.lower()
        if name_lower in self.SCS_DEBUG_REGISTERS:
            return self.SCS_DEBUG_REGISTERS[name_lower]
        return None
    
    def get_spr_control_reg(self, name):
        """Get SPR control register address by name"""
        name_lower = name.lower()
        if name_lower in self.SPR_CONTROL_REGISTERS:
            return self.SPR_CONTROL_REGISTERS[name_lower]
        return None
    
    def get_work_reg(self, name):
        """Get work register address by name"""
        name_lower = name.lower()
        if name_lower in self.WORK_REGISTERS:
            return self.WORK_REGISTERS[name_lower]
        return None
    
    def get_spr_reg(self, name):
        """Get SPR register address by name"""
        name_lower = name.lower()
        if name_lower in self.SPR_REGISTERS:
            return self.SPR_REGISTERS[name_lower]
        return None
    
    def is_debug_reg(self, name):
        """Check if register is a debug register"""
        return name.lower() in self.DEBUG_REGISTERS
    
    def is_scs_debug_reg(self, name):
        """Check if register is an SCS debug register"""
        return name.lower() in self.SCS_DEBUG_REGISTERS
    
    def is_spr_control_reg(self, name):
        """Check if register is an SPR control register"""
        return name.lower() in self.SPR_CONTROL_REGISTERS
    
    def is_work_reg(self, name):
        """Check if register is a work register"""
        return name.lower() in self.WORK_REGISTERS
    
    def is_spr_reg(self, name):
        """Check if register is an SPR register"""
        return name.lower() in self.SPR_REGISTERS
